The present invention relates to a semiconductor integrated circuit device and, more particularly, to effective technology to be applied to a semiconductor integrated circuit device having a SRAM (Static Random Access Memory) constituted by a memory cell CMOS type.
A SRAM memory cell of the CMOS type is composed of a flip-flop circuit comprising a pair of cross-connected (cross-coupled) CMOS circuits each of which consisting of a series connection of an n-channel drive MISFET and a p-channel load MISFET, and a pair of n-channel transfer MISFETs each of which connect a storage node of the flip-flop circuit to one of a pair of complementary data lines. The flip-flop circuit is supplied with the power source voltage Vcc and the ground potential, and a pair of data lines are respectively connected to the drain of the transfer MOSFETs wherein the common gate thereof becomes a word line. Operation of such memory cell of a known SRAM is effected in that the word line is raised and information (data) of "High" or "Low" from the data line is stored through the transfer MISFET to the storage node during the writing of data or information stored in the storage node is read through the transfer MISFET during the reading of data, thereby the memory cell functions as a static memory. In such a SRAM memory cell of the CMOS circuit, since leakage current of the MISFET only flows through the memory cell at the waiting state, the consumption power is quite low.
In the SRAM memory cell of the CMOS type, however, since one memory cell is constituted by a total of six MISFETs, a problem occurs in that the chip size becomes large. An attempt to solve such problems is discussed in connection with a memory cell called "Stacked CMOS" described in "IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-32, No. 2, FEBRUARY 1985, p. 273-277". The memory cell called "Stacked CMOS" is constituted by p-channel load MISFET of a flip-flop circuit formed to a polysilicon film on n-channel drive MISFET. Further describing the memory cell using FIGS. 1 and 2, n-channel drive MISFET formed in a silicon substrate is converted at an upper portion and a side surface of a gate electrode 3b by at least a thin insulation film 14, and further a polysilicon film is provided on an upper portion and a side surface thereof. Source 5e, drain 5b and a channel member 5d of p-channel load MISFET are formed in the polysilicon film. Gate electrode of the p-channel load MISFET is common to the gate electrode 3b of the n-channel drive MISFET just below the channel member 5d, and a thin insulative film 14 becomes a gate insulation film of the p-channel MISFET. The drive MISFET of the flip-flop circuit is constituted by n-type impurity area 1e forming the common source, n-type impurity areas 1c, 1d forming drain and gate electrodes 3b, 3c. Respective gate electrodes 3b, 3c are connected through connection holes 2b, 2a to impurity areas at drain side in cross connection. N-type impurity areas 1c, 1d forming drain of respective drive MISFETs are common to source of the n-channel transfer MISFET connected to the flip-flop circuit and constitute storage node of the flip-flop circuit, and the transfer MISFET is constituted by a gate electrode 3a common to the source impurity area and n-type impurity areas 1a, 1b forming drain. The n-type impurity areas 1a, 1b are connected through connection holes 8a, 8b to aluminium electrodes 9a, 9b. The common gate electrode 3a constitutes a word line in the memory, and the aluminium electrodes 9a, 9b constitute data lines, respectively. On low-resistance polysilicon films 5a, 5b where the p-type impurity forming drain of the p-channel load MISFET is added at high density and gate electrodes 3b, 3c of the drive MISFET, connection holes 8e, 8f are opened so that respective areas are exposed commonly. Aluminium electrodes 9c, 9d connect between the polysilicon film 5a and the gate electrode 3b and between the polysilicon film 5a and the gate electrode 3c, respectively. The source of the p-channel load MISFET comprises a common low resistance polysilicon film 5e to which a p-type impurity is added at high density, and the power source voltage Vcc is supplied to the source of the two p-channel MISFETs. Channel members 5c, 5d of the p-channel MISFETs are arranged on the gate electrodes 3c, 3d of the drive MISFET, respectively.